Integrated memory devices are commonly used in a multitude of applications for storing information. Particularly, the devices based on non-volatile memories allow preserving information even when a power supply is off; this category includes the flash E2PROMs, which must be erased in sectors (instead of one cell at a time).
Different communication protocols (with respective bus architectures) have been proposed in the last years for interfacing the memory devices with external units. Particular attention has been devoted to protocols that operate with a low number of signals, so as to limit the corresponding number of pins of the memory devices. An example of those protocols is the Low Pin Count (LPC) protocol.
The memory devices that are compliant with the LPC protocol include a communication interface operatively coupled with the flash memory. This interface bridges between the flash memory and an external bus, which has a transfer parallelism typically lower than an address parallelism and a data parallelism of the flash memory. The bus exploits a time division-multiplexing scheme, which allows exchanging information between the flash memory and the external units in chucks corresponding to its transfer parallelism. In this way, it is possible to reduce the cost and the size of the memory devices (but with a loss in their access and transfer rate).
However, the communication interfaces known in the art are not completely satisfactory. Particularly, the available solutions are not very flexible; this makes it rather complex to use the memory devices in some specific applications.
Particularly, the known memory devices do not exploit the performance of the corresponding flash memories at their best in applications requiring the repetition of consecutive operations relating to the sectors.
A typical example is an erase operation of the flash memory. In this respect, the sectors are logically grouped into blocks. The LPC protocol supports two different erase commands that can be used to erase a single sector or all the sectors of a block, respectively. A drawback of this solution is that the execution of erase operations on multiple sectors in succession involves a significant overload of the bus; indeed, the erase operations require two communication cycles on the bus for each sector to be erased; therefore, the bus remains busy for a period that is relatively long (with a detrimental effect on the operation of the external units).
Similar drawbacks are experienced when protection registers of the flash memory must be configured; as it is well known, each protection register is associated with a corresponding sector to specify whether the sector is locked or not for writing. Even in this case, the LPC protocol supports a command for writing the protection registers of a single sector or of all the sectors of a block; therefore, an overload of the bus is experienced when the protection registers of multiple sectors must be written in succession.
The above-mentioned drawbacks have been exacerbated by the modern data compression techniques, which have fostered a very high granularity of the flash memories (in terms of reduced size of the sectors). Indeed, the rate of the operations relating to the sectors increases accordingly with a corresponding negative impact on the performance of a whole system wherein the memory device is embedded.